A semiconductor device includes a large number of memory cells arranged along rows and columns which are orthogonal to each other. The density of defects generated in such a semiconductor memory device during manufacturing is relatively independent of the integration density of the device, but is dependent on the semiconductor manufacturing technology. The higher the integration density of the device,. The greater is the ration of the number of normal memory cells to that of defective memory cells. Even if the device, however, includes only one defective memory cell therein, the device cannot operate normally, and therefore, the device is abandoned (or discarded).
In order to be able to operate a semiconductor device despite such a defective memory cell, a semiconductor memory device incorporates a redundant memory cell array in the main memory cell array along the rows and columns. In a semiconductor memory device including such a redundancy memory cell array, the manufacturing yield can be improved.
The semiconductor memory device which comprises flash electrically erasable programmable read-only memory cells has an array divided into plural mats. Hereinafter, such a semiconductor memory device is named a flash memory device. Each mat of the flash memory device is divided into a plurality of sectors, each of which is an erase unit as well known to ones of ordinary skill in the art. In each sector, there is provided a main memory cell array of a first plurality of columns (referred to as "a main column" or "a main bit line") of main memory cells and a redundancy memory cell array of a second plurality of columns (or redundant columns) of redundant memory cells. In the flash memory device, there is incorporated a circuit for replacing a first column of at least one defective memory cell (or a defective column of memory cells) with a second column of redundant memory cells. Hereinafter, such a circuit is named a redundancy circuit. Since the redundancy circuit is provided in the prior flash memory device on the basis of each sector, the redundancy circuit thus incorporated therein occupies a large amount of an integrated circuit chip region. As a result, it results in a reduction of a chip efficiency.
As the integration density of the device becomes high, a minimum feature size may be reduced more and more, particularly in a memory cell array. For this, such a possibility that the first columns adjacent to each other can be short-circuited may become by far much. In the prior flash memory device, however, it is general a redundancy scheme that only one column of defective memory cells is repaired by means of only one address information indicating the column of the defective memory cells. Therefore, when two columns of main memory cells are short-circuited, address information corresponding to the two columns have to be stored in corresponding redundancy circuit is, respectively. This also results in a reduction of a chip efficiency.
Accordingly, it is needed a new redundancy architecture capable of repairing two adjacent columns thus short-circuited to each other by use of only one address information.